/* 
 * Copyright (c) 2019 Xilinx, Inc. 
 * All rights reserved.
 *
 * Author: Chris Lavin, Xilinx Research Labs.
 *  
 * This file is part of RapidWright. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 *     http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 * 
 */
/**
 * 
 */
package com.xilinx.rapidwright.device;


/**
 * Generated on: Fri Dec 06 10:46:56 2019
 * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
 * 
 * Enumeration of Site type for all valid devices within Vivado.
 */
public enum SiteTypeEnum {
	ABUS_SWITCH,
	AMS_ADC,
	AMS_DAC,
	BIAS,
	BITSLICE_COMPONENT_RX_TX,
	BITSLICE_CONTROL,
	BITSLICE_RXTX_RX,
	BITSLICE_RXTX_TX,
	BITSLICE_RX_TX,
	BITSLICE_TX,
	BLI_HBM_APB_INTF,
	BLI_HBM_AXI_INTF,
	BSCAN,
	BSCAN_JTAG_MONE2,
	BUFCE_LEAF,
	BUFCE_LEAF_X16,
	BUFCE_ROW,
	BUFCE_ROW_FSR,
	BUFG,
	BUFGCE,
	BUFGCE_DIV,
	BUFGCE_HDIO,
	BUFGCTRL,
	BUFG_GT,
	BUFG_GT_SYNC,
	BUFG_LB,
	BUFG_PS,
	BUFHCE,
	BUFIO,
	BUFMRCE,
	BUFR,
	CAPTURE,
	CFGIO_SITE,
	CFG_IO_ACCESS,
	CMACE4,
	CMAC_SITE,
	CONFIG_SITE,
	DCI,
	DCIRESET,
	DNA_PORT,
	DRP_AMS_ADC,
	DRP_AMS_DAC,
	DSP48E1,
	DSP48E2,
	EFUSE_USR,
	FE,
	FIFO18E1,
	FIFO18_0,
	FIFO36,
	FIFO36E1,
	FRAME_ECC,
	GCLK_TEST_BUF,
	GCLK_TEST_BUFE3,
	GLOBALSIG,
	GTHE2_CHANNEL,
	GTHE2_COMMON,
	GTHE3_CHANNEL,
	GTHE3_COMMON,
	GTHE4_CHANNEL,
	GTHE4_COMMON,
	GTM_DUAL,
	GTM_REFCLK,
	GTPE2_CHANNEL,
	GTPE2_COMMON,
	GTXE2_CHANNEL,
	GTXE2_COMMON,
	GTYE3_CHANNEL,
	GTYE3_COMMON,
	GTYE4_CHANNEL,
	GTYE4_COMMON,
	GTZE2_OCTAL,
	HARD_SYNC,
	HBM_REF_CLK,
	HDIOBDIFFINBUF,
	HDIOB_M,
	HDIOB_S,
	HDIOLOGIC_M,
	HDIOLOGIC_S,
	HDIO_BIAS,
	HDIO_VREF,
	HDLOGIC_CSSD,
	HPIOB,
	HPIOBDIFFINBUF,
	HPIOBDIFFOUTBUF,
	HPIOB_DCI_SNGL,
	HPIOB_M,
	HPIOB_S,
	HPIOB_SNGL,
	HPIO_RCLK_PRBS,
	HPIO_VREF_SITE,
	HPIO_ZMATCH_BLK_HCLK,
	HRIO,
	HRIODIFFINBUF,
	HRIODIFFOUTBUF,
	HSADC,
	HSDAC,
	IBUFDS_GTE2,
	ICAP,
	IDELAYCTRL,
	IDELAYE2,
	IDELAYE2_FINEDELAY,
	ILKNE4,
	ILKN_SITE,
	ILOGICE2,
	ILOGICE3,
	IN_FIFO,
	IOB,
	IOB18,
	IOB18M,
	IOB18S,
	IOB33,
	IOB33M,
	IOB33S,
	IOBM,
	IOBS,
	IOPAD,
	IPAD,
	ISERDESE2,
	KEY_CLEAR,
	LAGUNA,
	MMCM,
	MMCME2_ADV,
	MMCME3_ADV,
	MTBF2,
	MTBF3,
	ODELAYE2,
	ODELAYE2_FINEDELAY,
	OLOGICE2,
	OLOGICE3,
	OPAD,
	OSERDESE2,
	OUT_FIFO,
	PCIE40E4,
	PCIE4CE4,
	PCIE_2_1,
	PCIE_3_0,
	PCIE_3_1,
	PHASER_IN,
	PHASER_IN_ADV,
	PHASER_IN_PHY,
	PHASER_OUT,
	PHASER_OUT_ADV,
	PHASER_OUT_PHY,
	PHASER_REF,
	PHY_CONTROL,
	PLL,
	PLLE2_ADV,
	PLLE3_ADV,
	PLL_SELECT_SITE,
	PMV,
	PMV2,
	PMV2_SVT,
	PMVBRAM,
	PMVIOB,
	PS7,
	PS8,
	RAMB180,
	RAMB181,
	RAMB18E1,
	RAMB36,
	RAMB36E1,
	RAMBFIFO18,
	RAMBFIFO36,
	RAMBFIFO36E1,
	RIU_OR,
	SLICEL,
	SLICEM,
	STARTUP,
	SYSMONE1,
	SYSMONE4,
	TIEOFF,
	URAM288,
	USR_ACCESS,
	VBUS_SWITCH,
	VCU,
	XADC,
	XIPHY_FEEDTHROUGH,
}
